 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR FEATURES * 10 single ended LVCMOS/LVTTL outputs, 7 typical output impedance * Selectable CLK0 and CLK1 LVCMOS/LVTTL clock inputs * CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL * Maximum output frequency: 250MHz * Bank skew: 30ps (maximum) * Output skew: 175ps (maximum) * Part-to-part skew: 850ps (maximum) * Multiple frequency skew: 200ps (maximum) * 3.3V input, outputs may be either 3.3V or 2.5V supply * -40C to 85C ambient operating temperature * Pin compatible to the MPC9446 and MPC946 ICS87946I-147 GENERAL DESCRIPTION The ICS87946I-147 is a low skew, /1, /2 LVCMOS/LVTTL Clock Generator and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87946I-147 has two selectable single ended clock inputs. The single ended clock inputs accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines. ,&6 The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. . The ICS87946I-147 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply mode. Guaranteed bank, output and part-to-part skew characteristics make the ICS87946I-147 ideal for those clock distribution applications demanding well defined performance and repeatability. - BLOCK DIAGRAM CLK_SEL CLK0 CLK1 DIV_SELA 0 0 1 PIN ASSIGNMENT MR/nOE GND GND VDDA VDDA QA0 QA1 QA2 /1 /2 0 QA0:QA2 1 CLK_SEL VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 GND QB0 VDDB QB1 GND QB2 VDDB VDDC QB0:QB2 1 CLK0 CLK1 DIV_SELA DIV_SELB 0 ICS87946I-147 21 20 19 18 17 DIV_SELB QC0:QC3 1 DIV_SELC GND DIV_SELC MR/nOE 32-Lead LQFP 7mm x 7mm x 1.4mm body package Y Package Top View 87946AYI-147 VDDC QC0 GND QC1 VDDC QC2 GND QC3 www.icst.com/products/hiperclocks.html 1 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR Type Input Power Input Input Input Input Power Power Output Description Clock select input. When HIGH, selects CLK1. Pulldown When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Positive supply pin. LVCMOS / LVTTL clock inputs. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Positive supply pins for Bank C outputs. Pullup ICS87946I-147 TABLE 1. PIN DESCRIPTIONS Number 1 2 3, 4 5 6 7 8, 11, 15, 20, 24, 27, 31 9, 13, 17 10, 12, 14, 16 18, 22 Name CLK_SEL VDD CLK0, CLK1 DIV_SELA DIV_SELB DIV_SELC GND VDDC QC0, QC1, QC2, QC3 VDDB Bank C outputs. LVCMOS / LVTTL interface levels. 7 typical output impedance. Power Positive supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 19, 21, 23 QB2, QB1, QB0 Output 7 typical output impedance. 25, 29 VDDA Power Positive supply pins for Bank A outputs. Bank A outputs. LVCMOS / LVTTL interface levels. 26, 28, 30 QA2, QA1, QA0 Output 7 typical output impedance. Active HIGH Master Reset. Active LOW output enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated 32 MR/nOE Input Pulldown (HiZ). When logic LOW the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance VDD, *VDDx = 3.6V 51 51 25 7 Test Conditions Minimum Typical Maximum 4 Units pF K K pF *NOTE: VDDx denotes VDDA, VDDB, VDDC. TABLE 3. FUNCTION TABLE MR/nOE 1 0 0 0 0 0 0 87946AYI-147 DIV_SELA X 0 1 X X X X Inputs DIV_SELB X X X 0 1 X X DIV_SELC X X X X X 0 1 QA0:QA2 Hi Z fIN/1 fIN/2 Active Active Active Active Outputs QB0:QB2 Hi Z Active Active fIN/1 fIN/2 Active Active QC0:QC3 Hi Z Active Active Active Active fIN/1 fIN/2 REV. A APRIL 21, 2003 www.icst.com/products/hiperclocks.html 2 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR 4.6V -0.5V to VDD + 0.5 V -0.5V to VDDx + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ICS87946I-147 ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C Symbol VDD VDDx IDD IDDx Parameter Positive Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current Test Conditions Minimum 3.0 3.0 Typical 3.3 3.3 Maximum 3.6 3.6 55 23 Units V V mA mA NOTE 1: VDDx denotes VDDA, VDDB, VDDC. TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, MR/nOE CLK0, CLK1 Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.6V VDD = VIN = 3.6V VDD = 3.6V, VIN = 0V VDD = 3.6V, VIN = 0V -5 -150 2.6 0.5 -5 5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V A A VIH VIL Input Low Voltage IIH Input High Current IIL VOH VOL IOZL IOZH Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit. 87946AYI-147 www.icst.com/products/hiperclocks.html 3 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR Test Conditions f 250MHz Measured on rising edge at VDDx/2 Minimum 2 Typical Maximum 250 5 30 Units MHz ns ps ps ps ps ps ns ns ns ICS87946I-147 TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V 0.3V, TA = -40C TO 85C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 tsk(b) tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at VDDx/2 175 Multiple Frequency Skew; tsk(w) Measured on rising edge at VDDx/2 275 NOTE 4, 7 tsk(pp) Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge at VDDx/2 850 Output Rise/Fall Time; tR / t F 20% to 80% 400 950 NOTE 6 tPW Output Pulse Width tPERIOD/2 - 1 tPERIOD/2 tPERIOD/2 + 1 Output Enable Time; tEN f = 10MHz 3 NOTE 6 Output Disable Time; tDIS f = 10MHz 3 NOTE 6 NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDX = 2.5V 5%, TA = -40C TO 85C Symbol VDD VDDx IDD IDDx Parameter Positive Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 55 22 Units V V mA mA NOTE 1: VDDx denotes VDDA, VDDB, VDDC. 87946AYI-147 www.icst.com/products/hiperclocks.html 4 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR Test Conditions Minimum 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 1.8 0.5 -5 5 Typical Maximum VDD + 0.3 VDD + 0.3 0.8 1.3 150 5 Units V V V V A A A A V V A A ICS87946I-147 TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5%, VDDX = 2.5V 5%, TA = -40C TO 85C Symbol Parameter Input High Voltage DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, nMR/OE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, nMR/OE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, nMR/OE CLK0, CLK1 DIV_SELA, DIV_SELB, DIV_SELC, CLK_SEL, nMR/OE CLK0, CLK1 VIH VIL Input Low Voltage IIH Input High Current IIL VOH VOL IOZL IOZH Input Low Current Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Tristate Current Low Output Tristate Current High NOTE 1: Outputs terminated with 50 to VDDx/2. See Parameter Measurement Section, 3.3V/2.5V Output Load Test Circuit. TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDX = 2.5V 5%, TA = -40C TO 85C Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 f 250MHz Measured on rising edge at VDDx/2 2 Test Conditions Minimum Typical Maximum 250 5 35 Units MHz ns ps ps ps ps ps ns ns ns tsk(b) tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge at VDDx/2 175 Multiple Frequency Skew; tsk(w) Measured on rising edge at VDDx/2 200 NOTE 4, 7 tsk(pp) Par t-to-Par t Skew; NOTE 5, 7 Measured on rising edge at VDDx/2 875 Output Rise/Fall Time; tR / tF 20% to 80% 400 950 NOTE 6 Output Pulse Width tPERIOD/2 - 1 tPERIOD/2 tPERIOD/2 + 1 tPW Output Enable Time; f = 10MHz 3 tEN NOTE 6 Output Disable Time; tDIS f = 10MHz 3 NOTE 6 NOTE 1: Measured from the VDD/2 of the input to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. 87946AYI-147 www.icst.com/products/hiperclocks.html 5 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR ICS87946I-147 PARAMETER MEASUREMENT INFORMATION VDD, VDDx = 1.65V0.15V 2.05V5% 1.25V5% SCOPE LVCMOS Qx V DD VDDx SCOPE Qx LVCMOS GND = -1.65V0.15V GND = -1.25V5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT PART 1 Qx V DDx V DDx 2 Qx 2 PART 2 Qy V DDx V DDx 2 tsk(pp) Qy 2 tsk(o) PART-TO-PART SKEW OUTPUT SKEW CLK0, CLK1 VDDx 2 80% 80% 20% Clock Outputs VDDx 2 t PD 20% t R t F QAx,QBx, QCx PROPAGATION DELAY OUTPUT RISE/FALL TIME VDDx VDDx 2 t PW t PERIOD VDDx 2 QAx, QBx, QCx 2 odc = t PW t PERIOD tPW & tPERIOD 87946AYI-147 www.icst.com/products/hiperclocks.html 6 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION ICS87946I-147 TABLE 6. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS87946I-147 is: 1204 87946AYI-147 www.icst.com/products/hiperclocks.html 7 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR ICS87946I-147 PACKAGE OUTLINE - Y SUFFIX TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L q ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM Reference Document: JEDEC Publication 95, MS-026 87946AYI-147 www.icst.com/products/hiperclocks.html 8 REV. A APRIL 21, 2003 Integrated Circuit Systems, Inc. LOW SKEW, /1, /2 LVCMOS/LVTTL CLOCK GENERATOR Marking 87946AI147 87946AI147 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C ICS87946I-147 TABLE 8. ORDERING INFORMATION Part/Order Number ICS87946AYI-147 ICS87946AYI-147T While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87946AYI-147 www.icst.com/products/hiperclocks.html 9 REV. A APRIL 21, 2003 |
Price & Availability of ICS87946I-147
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |